The inventive concept relates to a semiconductor device, and more particularly, to a voltage-controlled oscillator (VCO) circuit which may generate an output frequency with regard to even a low input voltage by performing a level shifting operation on the input voltage and may prevent a malfunction of a divider, which is caused by a high input voltage, and a semiconductor device including the VCO circuit.
When digital signals are transmitted using digital clocks, ranges for determining logic values 0 and 1 have to be accurately defined in advance in order to clearly determine whether an input signal has the value 0 or 1. That is, the start and end points of one clock have to be clearly determined. However, when signals are transmitted in a wired or wireless environment, a delay of a signal occurs according to a path of the signal such that a phase of the signal naturally changes. Thus, the start and end points for distinguishing between the values 0 and 1 by a reception terminal may become unclear.
As a result, a circuit for synchronizing the start and end points of a clock received by the reception terminal, with those of a clock transmitted by a transmission terminal, is required. A phase-locked loop (PLL) circuit functions to match a start (0°) and an end (360°) of a period of a clock. Regardless of how a signal is input, the PLL circuit functions to lock the signal as if the signal is input from a certain phase point.
Also, the PLL circuit is used in an analog circuit, such as a radio frequency (RF) circuit, as well as a digital circuit. In the analog circuit, the PLL circuit is used to prevent a frequency being used as a source from oscillating. A frequency generated by a VCO is largely influenced by its environment. Thus, in many cases, an output frequency is slightly oscillated and is modified into a frequency having a different range from that of the output frequency.
In this case, a system may not normally operate. Particularly, in a modern wireless communication system that has to finely divide and use frequencies, frequency stability is very important.
Furthermore, the PLL circuit functions to tune frequencies. In more detail, an output frequency may vary into a desired frequency by modifying a predetermined portion of the PLL circuit.
FIG. 1 is a schematic block diagram of a PLL circuit 100. FIG. 2 is a graph showing a correlation between an input voltage Vctrl and an output frequency Fout of a VCO 110 illustrated in FIG. 1. FIGS. 3A and 3B are graphs illustrating an operation of a divider 112 illustrated in FIG. 1.
Referring to FIG. 1, the PLL circuit 100 includes a temperature-compensated crystal oscillator (TCXO) 102, a phase detector (P/D) 104, a charge pump 106, a loop filter 108, the VCO 110, and the divider 112.
The TCXO 102 generates a reference frequency fref. The P/D 104 compares the reference frequency fref to a divided frequency fdiv output from the divider 112, outputs an up pulse signal UP if the reference frequency fref leads the divided frequency fdiv, and outputs a down pulse signal DN if the reference frequency fref lags behind the divided frequency fdiv. The charge pump 106 functions to convert the up pulse signal UP or the down pulse signal DN output from the P/D 104 into a voltage level. The loop filter 108 generally has a structure of a low-pass filter (LPF) and functions to accumulate and then emit charges from the charge pump 106 and to remove noise frequencies including undesired output components.
The VCO 110 outputs the output frequency Fout corresponding to the input voltage Vctrl. For example, if a voltage of 1.9V is input, a frequency of 790 megahertz (MHz) may be output, if a voltage of 2.0V is input, a frequency of 800 MHz may be output, and, if a voltage of 2.1V is input, a frequency of 810 MHz may be output. That is, the VCO 110 outputs the output frequency Fout corresponding to the input voltage Vctrl, as illustrated in FIG. 2.
The divider 112 functions to divide the output frequency Fout output from the VCO 110 based on a divide ratio, so as to output the divided frequency fdiv. If the divide ratio is 1/M, fdiv=Fout/M. The operation of the divider 112 may be represented as illustrated in FIGS. 3A and 3B. In more detail, the divider 112 converts a relatively high frequency, as illustrated in FIG. 3A, into a relatively low frequency, as illustrated in FIG. 3B.
A function of locking a frequency will now be described.
If a temperature changes and thus the output frequency Fout is not accurately output from the VCO 110, the P/D 104 compares a phase of the output frequency Fout to that of the reference frequency fref through a feedback. The P/D 104 outputs the up pulse signal UP if the reference frequency fref leads the fed-back divided frequency fdiv, and outputs the down pulse signal DN if the reference frequency fref lags behind the fed-back divided frequency fdiv. In this case, as a phase difference is large, a size of the up pulse signal UP or the down pulse signal DN is constant, however, a width of the up pulse signal UP or the down pulse signal DN varies in proportion to a size of the phase difference. Since the input voltage Vctrl of the VCO 110 has a predetermined voltage level, the up pulse signal UP or the down pulse signal DN which is output from the P/D 104 needs to be converted into the input voltage Vctrl of the VCO 110, by the charge pump 106.
However, if the reference frequency fref generated by the TCXO 102 is a high frequency, even a slight influence may vary the output frequency Fout. Thus, the phase difference needs to be compared to a low frequency that may be relatively easily compared. That is, the divider 112 provides the output frequency Fout of the VCO 110 by accurately reducing the output frequency Fout by a predetermined ratio.
By way of example, if the output frequency Fout of the VCO 110 is 800 MHz and the divider 112 uses a 1/100 divide ratio, a signal of 8 MHz is input to the P/D 104. Thus, the reference frequency fref of 8 MHz may be used. Since a TCXO is not significantly influenced by an external temperature so as to be able to stably output a frequency, the TCXO 102 generates the reference frequency fref.
The PLL circuit 100 may vary the output frequency Fout using the divider 112. If the divided frequency fdiv input to the P/D 104 is slightly modified, the output frequency Fout may be stable at another frequency.
For example, if the output frequency Fout of 800 MHz is generated using the reference frequency fref of 8 MHz, the divider 112 uses a 1/100 divide ratio. If the divider 112 uses a 1/99 divide ratio, the divided frequency fdiv is 8.08 MHz and the P/D 104 generates a pulse signal with a difference of 80 kilohertz (kHz).
If the above situation continues, the output frequency Fout that is ultimately output from the VCO 110 is locked to be 792 MHz, and the divided frequency fdiv that is output from the divider 112 using a 1/99 divide ratio is locked to be 792/99=8 MHz.
However, if the input voltage Vctrl is lower than a predetermined voltage level, the VCO according to a conventional approach may not operate. In more detail, the VCO 110 may not operate in an area which is indicated by “c” of FIG. 2 and where the input voltage Vctrl is lower than a threshold voltage Vth of a transistor that receives and uses the input voltage Vctrl as a gate voltage.
Also, as indicated by “a”, “b”, and “c” of FIG. 2, the VCO 110 according to the conventional art generates the output frequency Fout in proportion to the input voltage Vctrl regardless of the voltage level of the input voltage Vctrl, and thus, a voltage larger than a predetermined voltage level may be input so as to generate an excessively high frequency. In this case, the divider 112 may not perform a normal frequency dividing operation as illustrated in FIGS. 3A and 3B and a malfunction of the divider 112 may be caused due to a limitation of frequency speed.